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| Freescale Semiconductor, Inc. MC68HC05SU3A MC68HC05SU3A/H REV. 3 Freescale Semiconductor, Inc... TECHNICAL DATA HC05 MC68HC05SU3A TECHNICAL DATA For More Information On Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS 1 2 3 4 5 6 7 8 9 10 11 Freescale Semiconductor, Inc... TPG For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS Freescale Semiconductor, Inc... 10 11 TPG For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05SU3A Freescale Semiconductor, Inc... High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Unit TPG For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Conventions Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; `u' is used to indicate an undefined state (on reset). TPG For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number TITLE Page Number Freescale Semiconductor, Inc... 1 GENERAL DESCRIPTION 1.1 1.2 1.3 Features.................................................................................................................1-1 Mask Options.........................................................................................................1-2 MCU Structure.......................................................................................................1-2 2 PIN DESCRIPTIONS 2.1 Functional Pin Descriptions ...................................................................................2-1 2.2 OSC1 and OSC2 Connections ..............................................................................2-2 2.2.1 Crystal Oscillator..............................................................................................2-3 2.2.2 External Clock..................................................................................................2-3 2.2.3 RC Oscillator Option ........................................................................................2-4 2.3 Pin Assignments ....................................................................................................2-5 3 INPUT/OUTPUT PORTS 3.1 3.1.1 3.1.2 3.2 3.3 3.4 3.5 3.5.1 Parallel Ports..........................................................................................................3-1 Port Data Registers..........................................................................................3-1 Port Data Direction Registers ..........................................................................3-2 Port A -- Keyboard Interrupts (KBI) ......................................................................3-2 PD6 -- IRQ2..........................................................................................................3-2 Programmable Current Drive .................................................................................3-3 Programmable Pull-Up Devices.............................................................................3-3 Port Option Register ........................................................................................3-3 4 MEMORY AND REGISTERS 4.1 I/O Registers..........................................................................................................4-1 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com i Freescale Semiconductor, Inc. Paragraph Number 4.2 4.3 4.4 4.5 Page Number TITLE RAM ......................................................................................................................4-1 ROM ......................................................................................................................4-1 Memory Map .........................................................................................................4-2 I/O Registers Summary .........................................................................................4-3 Freescale Semiconductor, Inc... 5 RESETS AND INTERRUPTS 5.1 RESETS ................................................................................................................5-1 5.1.1 Power-On Reset (POR) ...................................................................................5-1 5.1.2 RESET Pin.......................................................................................................5-1 5.1.3 Low Voltage Reset (LVR) .................................................................................5-2 5.2 INTERRUPTS........................................................................................................5-2 5.2.1 Non-maskable Software Interrupt (SWI) ..........................................................5-3 5.2.2 Maskable Hardware Interrupts.........................................................................5-5 5.2.2.1 External Interrupt (IRQ)..............................................................................5-5 5.2.2.2 External Interrupt 2 (IRQ2).........................................................................5-7 5.2.2.3 Timer Interrupt............................................................................................5-7 5.2.2.4 Keyboard Interrupt (KBI) ............................................................................5-8 6 TIMER 6.1 6.2 6.3 6.4 Timer Overview .....................................................................................................6-1 Timer Control Register (TCR)................................................................................6-3 Timer Data Register (TDR)....................................................................................6-4 Operation during Low Power Modes .....................................................................6-4 7 CPU CORE AND INSTRUCTION SET 7.1 Registers ...............................................................................................................7-1 7.1.1 Accumulator (A) ...............................................................................................7-1 7.1.2 Index register (X) .............................................................................................7-2 7.1.3 Program counter (PC)......................................................................................7-2 7.1.4 Stack pointer (SP)............................................................................................7-2 7.1.5 Condition code register (CCR).........................................................................7-2 7.2 Instruction set ........................................................................................................7-3 7.2.1 Register/memory Instructions ..........................................................................7-4 7.2.2 Branch instructions ..........................................................................................7-4 7.2.3 Bit manipulation instructions ............................................................................7-4 7.2.4 Read/modify/write instructions.........................................................................7-4 7.2.5 Control instructions ..........................................................................................7-4 TPG ii For More Information On This Product, Go to: www.freescale.com MC68HC05SU3A Freescale Semiconductor, Inc. Paragraph Number Page Number TITLE Freescale Semiconductor, Inc... 7.2.6 Tables...............................................................................................................7-4 7.3 Addressing modes .................................................................................................7-11 7.3.1 Inherent............................................................................................................7-11 7.3.2 Immediate ........................................................................................................7-11 7.3.3 Direct................................................................................................................7-11 7.3.4 Extended..........................................................................................................7-12 7.3.5 Indexed, no offset.............................................................................................7-12 7.3.6 Indexed, 8-bit offset..........................................................................................7-12 7.3.7 Indexed, 16-bit offset........................................................................................7-12 7.3.8 Relative ............................................................................................................7-13 7.3.9 Bit set/clear ......................................................................................................7-13 7.3.10 Bit test and branch ...........................................................................................7-13 8 LOW POWER MODES 8.1 8.2 8.3 STOP Mode ...........................................................................................................8-1 WAIT Mode ............................................................................................................8-1 SLOW Mode ..........................................................................................................8-3 9 OPERATING MODES 9.1 9.2 User Mode .............................................................................................................9-1 Self-Check Mode ...................................................................................................9-1 10 ELECTRICAL SPECIFICATIONS 10.1 10.2 10.3 10.4 Maximum Ratings ................................................................................................10-1 Thermal Characteristics.......................................................................................10-1 DC Electrical Characteristics ...............................................................................10-2 Control Timing .....................................................................................................10-3 11 MECHANICAL SPECIFICATIONS 11.1 11.2 11.3 40-Pin DIP Package (Case 711-03).....................................................................11-2 42-Pin SDIP Package (Case 858-01) ..................................................................11-2 44-pin QFP Package (Case 824A-01) .................................................................11-3 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY TPG iv For More Information On This Product, Go to: www.freescale.com MC68HC05SU3A Freescale Semiconductor, Inc. LIST OF FIGURES Figure Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 5-1 5-2 5-3 5-4 6-1 7-1 7-2 8-1 9-1 11-1 11-2 1-3 TITLE Page Number Freescale Semiconductor, Inc... MC68HC05SU3A Block Diagram ...........................................................................1-3 Oscillator Connections............................................................................................2-3 Typical Oscillator Frequency for Selected External Resistor ..................................2-4 Typical Oscillator Frequency for Wire-Strap Connection ........................................2-4 Pin Assignment for 40-pin PDIP .............................................................................2-5 Pin Assignment for 42-pin SDIP .............................................................................2-6 Pin Assignment for 44-pin QFP ..............................................................................2-6 Port I/O Circuitry .....................................................................................................3-2 MC68HC05SU3A Memory Map .............................................................................4-2 Interrupt Stacking Order .........................................................................................5-3 Hardware Interrupt Processing Flowchart ..............................................................5-4 External Interrupt....................................................................................................5-6 Keyboard Interrupt Circuitry....................................................................................5-8 Timer Block Diagram ..............................................................................................6-2 Programming model ...............................................................................................7-1 Stacking order ........................................................................................................7-2 STOP and WAIT Mode Flowcharts.........................................................................8-2 MC68HC05SU3A Self-Check Circuit......................................................................9-2 40-pin DIP Package..............................................................................................11-2 42-pin SDIP Package ...........................................................................................11-2 44-pin QFP Package ............................................................................................11-3 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY TPG vi For More Information On This Product, Go to: www.freescale.com MC68HC05SU3A Freescale Semiconductor, Inc. LIST OF TABLES Table Number 1-1 3-1 4-1 5-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 9-1 9-2 10-1 10-2 TITLE Page Number Freescale Semiconductor, Inc... Power-On Reset Delay Mask Option ......................................................................1-2 I/O Pin Functions ....................................................................................................3-1 MC68HC05SU3A I/O Registers .............................................................................4-3 Reset/Interrupt Vector Addresses ..........................................................................5-3 MUL instruction.......................................................................................................7-5 Register/memory instructions.................................................................................7-5 Branch instructions .................................................................................................7-6 Bit manipulation instructions...................................................................................7-6 Read/modify/write instructions ...............................................................................7-7 Control instructions.................................................................................................7-7 Instruction set .........................................................................................................7-8 M68HC05 opcode map...........................................................................................7-10 Mode Selection.......................................................................................................9-1 Self-Check Report ..................................................................................................9-3 DC Electrical Characteristics ................................................................................10-2 Control Timing ......................................................................................................10-3 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com vii Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY TPG viii For More Information On This Product, Go to: www.freescale.com MC68HC05SU3A Freescale Semiconductor, Inc. 1 1 GENERAL DESCRIPTION The MC68HC05SU3A HCMOS microcontroller is a member of the M68HC05 family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, I/O, and Timer. The MC68HC05SU3A is pin compatible with the MC6805U3 and is provided as a low power upgrade path for MC6805U3 applications. The low power advantage of CMOS is combined with the addition of I/O and port modifications which help eliminate external components in cost sensitive applications. Freescale Semiconductor, Inc... 1.1 * * * * * * * * * * * * * * * * Features Fully static chip design featuring the industry standard 8-bit M68HC05 core Pin compatible with the MC6805U3 Power saving STOP, WAIT, and SLOW modes 3840 bytes of user ROM with security feature 192 bytes of user RAM (64 bytes for stack) 32 bidirectional I/O lines Keyboard interrupts 8-bit count-down timer with programmable 7-bit prescaler On-chip crystal oscillator, with built-in capacitor for RC option Second software programmable external interrupt line (IRQ2) Direct LED drive capability on all ports Programmable 20K pull-up resistors integrated into I/O ports (1.9K pull-up resistors integrated into PB0 and PB1) Internal 60K pull-up resistor on RESET pin Internal 100K pull-up resistor on IRQ pin Low Voltage Reset Available in 40-pin PDIP, 42-pin SDIP and 44-pin QFP packages TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com GENERAL DESCRIPTION 1-1 Freescale Semiconductor, Inc. 1 1.2 Mask Options The following mask options are available: * * * RC or Crystal Oscillator (see Section 2.2). The default is crystal option. IRQ pull-up resistor -- enabled or disabled. Power-On Reset delay -- Table 1-1 shows available options. The default value is 4096 cycles. Freescale Semiconductor, Inc... Table 1-1 Power-On Reset Delay Mask Option Power-On Reset Delay (cycles) 256 512 1024 2048 4096 8192 16384 32768 * Power-On Reset Slow mode. If enabled, the device goes into Slow mode directly upon power-on reset. The bus frequency is 16 times slower than the normal mode. Thus, the power-on reset delay will also be 16 times longer. The default setting is "Slow mode" disabled. 1.3 MCU Structure Figure 1-1 shows a block diagram of the MC68HC05SU3A MCU. TPG 1-2 For More Information On This Product, Go to: www.freescale.com GENERAL DESCRIPTION MC68HC05SU3A Freescale Semiconductor, Inc. 1 PORT A USER ROM - 3840 BYTES SELF-CHECK - 240 BYTES RAM - 192 BYTES DDR A KEYBOARD INTERRUPT 8 PA0 - PA7 Freescale Semiconductor, Inc... PORT B DDR B 7 0 ACCUMULATOR 8 PB0 - PB7 M68HC05 CPU 7 0 INDEX REGISTER 12 5 0000011 15 4 0 STACK POINTER PORT C 0 DDR C 8 PC0 - PC7 PROGRAM COUNTER IRQ RESET RESET 7 0 111HINZC CONDITION CODE REGISTER POWER 8-BIT COUNTER VDD VSS OSC1 OSC2 TIMER TIMER CONTROL DDR D 7-BIT PRESCALER PORT D LOW VOLTAGE RESET PD7 PD6/IRQ2 PD5 PD4 PD3 PD2 PD1 PD0 OSC /2 Figure 1-1 MC68HC05SU3A Block Diagram TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com GENERAL DESCRIPTION 1-3 Freescale Semiconductor, Inc. 1 Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY TPG 1-4 For More Information On This Product, Go to: www.freescale.com GENERAL DESCRIPTION MC68HC05SU3A Freescale Semiconductor, Inc. 2 2 PIN DESCRIPTIONS This section provides a description of the functional pins of the MC68HC05SU3A microcontroller. Freescale Semiconductor, Inc... 2.1 Functional Pin Descriptions 40-pin PDIP PIN No. 4 1 -- -- 7 42-pin SDIP PIN No. 5 -- 1 2 8 44-pin QFP PIN No. 10, 33 32 6 7 13 PIN NAME VDD VSS VSS(INT) VSS(EXT) VPP DESCRIPTION Power is supplied to the MCU using these pins. VDD should be connected to the positive supply. VSS, VSS(INT), and VSS(EXT) should be connected to supply ground. This is not used, it should be connected to VDD or VSS. IRQ is software programmable to provide two choices of interrupt triggering sensitivity. These options are: 1) negative-edge-sensitive triggering only, or 2) both negative-edge-sensitive and level-sensitive triggering. This pin has an integrated pull-up resistor to VDD but should be tied to VDD if not needed to improve noise immunity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin may affect the mode of operation as described in Section 9. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. It also has an internal pull-down device that pulls the RESET pin low during the power-on reset cycles and an integrated pull-up resistor to VDD. The TIMER pin provides an optional gating input to the timer. Refer to Section 6 for additional information. The OSC1 and OSC2 pins are the connections for the on-chip oscillator. See Section 2.2 for detail. IRQ 3 4 9 RESET 2 3 8 TIMER OSC1, OSC2 8 5, 6 9 6, 7 14 11, 12 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com PIN DESCRIPTIONS 2-1 Freescale Semiconductor, Inc. 40-pin PDIP PIN No. 42-pin SDIP PIN No. 44-pin QFP PIN No. 2 PIN NAME DESCRIPTION These eight I/O lines comprise port A. The state of any pin is software programmable. All port A lines are configured as input during power-on or external reset. PA0-PA7 are also associated with the Keyboard Interrupt function. Each pin is equipped with a programmable integrated 20K pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. See Section 3 for details on the I/O ports. These eight I/O lines comprise port B. The state of any pin is software programmable. All port B lines are configured as input during power-on or external reset. PB0 and PB1 are equipped with an integrated 1.9K pull-up resistor. PB2-PB7 are equipped with a programmable integrated 20K pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. PB5-PB7 can also be programmed to provide a lower current drive of 2mA. See Section 3 for details on the I/O ports. These eight I/O lines comprise port C. The state of any pin is software programmable. All port C lines are configured as input during power-on or external reset. Each pin is equipped with a programmable integrated 20K pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. See Section 3 for details on the I/O ports. These eight I/O lines comprise port D. The state of any pin is software programmable. All port D lines are configured as input during power-on or external reset. Each pin is equipped with a programmable integrated 20K pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. PD6 is configured as IRQ2 by setting IRQ2E in the Miscellaneous Control Register ($0C). See Section 3 for details on the I/O ports. PA0-PA7 33-40 34-41 42-44, 1-5 Freescale Semiconductor, Inc... PB0-PB7 25-32 26-33 31, 35-41 PC0-PC7 9-16 10-17 15-22 PD0-PD7 24-21, 20-17 25-22, 21-18 30-23 IRQ2 18 19 24 2.2 OSC1 and OSC2 Connections The OSC1 and OSC2 pins are the connections for the on-chip oscillator -- the following configurations are available: 1) A crystal or ceramic resonator as shown in Figure 2-1(a). 2) An external clock signal as shown in Figure 2-1(b). 3) RC options as shown in Figure 2-1(c) and Figure 2-1(d). The external oscillator clock frequency, fOSC, is divided by two to produce the internal operating frequency, fOP. TPG 2-2 For More Information On This Product, Go to: www.freescale.com PIN DESCRIPTIONS MC68HC05SU3A Freescale Semiconductor, Inc. MCU OSC1 10M OSC2 OSC1 MCU OSC2 2 Unconnected External Clock 25p 25p Freescale Semiconductor, Inc... (a) Crystal or ceramic resonator connections VDD OSC2 R Unconnected (c) RC option 1 - external resistor (b) External clock source connection MCU OSC1 MCU OSC1 OSC2 (d) RC option 2 - internal resistor Figure 2-1 Oscillator Connections 2.2.1 Crystal Oscillator The circuit in Figure 2-1(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An external start-up resistor of approximately 10M is needed between OSC1 and OSC2 for the crystal type oscillator. 2.2.2 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 2-1(b). TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com PIN DESCRIPTIONS 2-3 Freescale Semiconductor, Inc. 2.2.3 RC Oscillator Option 2 This configuration is intended to be the lowest cost option in applications where oscillator accuracy is not important. An internal constant current source and a capacitor have been integrated on-chip, connected between the OSC2 pin and VSS. Thus by either connecting a resistor to VDD from OSC2 or by putting a wire strap between OSC1 and OSC2 self-oscillations at the frequency as shown in Figure 2-2 and Figure 2-3 can be induced. Freescale Semiconductor, Inc... 3.5 Oscillator Frequency (MHz) 3.0 2.5 2.0 1.5 1.0 50 70 90 110 130 150 170 190 210 230 Resistance (K) Figure 2-2 Typical Oscillator Frequency for Selected External Resistor 2.25 Oscillator Frequency (MHz) 2.00 1.75 T=0C T=25C T=50C 1.50 1.25 1.00 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 Figure 2-3 Typical Oscillator Frequency for Wire-Strap Connection TPG 2-4 For More Information On This Product, Go to: www.freescale.com PIN DESCRIPTIONS MC68HC05SU3A Freescale Semiconductor, Inc. 2.3 Pin Assignments 2 VSS RESET IRQ VDD OSC1 OSC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PD0 PD1 PD2 PD3 Freescale Semiconductor, Inc... VPP TIMER PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD7 PD6/IRQ2 PD5 PD4 Figure 2-4 Pin Assignment for 40-pin PDIP TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com PIN DESCRIPTIONS 2-5 Freescale Semiconductor, Inc. 2 Freescale Semiconductor, Inc... VSS(INT) VSS(EXT) RESET IRQ VDD OSC1 OSC2 VPP TIMER PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD7 PD6/IRQ2 PD5 PD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PD0 PD1 PD2 PD3 Figure 2-5 Pin Assignment for 42-pin SDIP 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 NC PA3 PA4 PA5 PA6 PA7 VSS(INT) VSS(EXT) RESET IRQ VDD OSC1 VDD VSS PB0 PD0 PD1 PD2 PD3 PD4 PD5 PD6/IRQ2 PD7 Figure 2-6 Pin Assignment for 44-pin QFP OSC2 VPP TIMER PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 TPG 2-6 For More Information On This Product, Go to: www.freescale.com PIN DESCRIPTIONS MC68HC05SU3A Freescale Semiconductor, Inc. 3 INPUT/OUTPUT PORTS The MC68HC05SU3A has 32 bidirectional I/O lines, arranged as four 8-bit I/O ports (Port A, B, C, and D). The individual bits in these ports are programmable as either inputs or outputs under software control by the Data Direction Registers (DDRs). All port pins (except PB0 and PB1) each has an associated 20K pull-up resistor, which can be connected/disconnected under software control. Also, each port pin (except PB0 and PB1) is capable of sinking and driving a maximum current of 10mA (e.g. direct drive for LEDs). PB0 and PB1 each has a permanent 1.9K pull-up resistor connected, with 20mA current sink capability. Port A can also be configured for keyboard interrupts. 3 Freescale Semiconductor, Inc... 3.1 Parallel Ports Port A, B, C, and D are 8-bit bidirectional ports. Each Port pin is controlled by the corresponding bits in a Data Direction Register and a Data Register as shown in Figure 3-1. The functions of the I/O pins are summarized in Table 3-1. Table 3-1 I/O Pin Functions R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Function The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read. 3.1.1 Port Data Registers Each Port I/O pin has a corresponding bit in the Port Data Register. When a Port I/O pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. All Port I/O pins can drive a current of 10mA when programmed as outputs. When a Port pin is programmed as an input, any read of the Port Data Register will return the logic state of the corresponding I/O pin. The locations of the Data Registers for Port A, B, C, and D are at $00, $01, $02, and $03 respectively. The Port Data Registers are unaffected by reset. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com INPUT/OUTPUT PORTS 3-1 Freescale Semiconductor, Inc. DATA DIRECTION REGISTER BIT 3 INTERNAL MC68HC05 CONNECTIONS LATCHED OUTPUT DATA BIT OUTPUT I/O PIN Freescale Semiconductor, Inc... INPUT REGISTER BIT INPUT I/O Figure 3-1 Port I/O Circuitry 3.1.2 Port Data Direction Registers Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, C, and D are located at $04, $05, $06 and, $07 respectively. The DDRs are cleared by reset. Note: A "glitch" may occur on an I/O pin when selecting from an input to an output unless the data register is first preconditioned to the desired state before changing the corresponding DDR bit from a "0" to a "1". 3.2 Port A -- Keyboard Interrupts (KBI) Port A is configured for use as keyboard interrupts when the KBIE bit is set in the Miscellaneous Control Register (MCR). Individual keyboard interrupt port pins are also maskable by setting corresponding bits in the Keyboard Interrupt Mask Register. See Section 5.2.2.4 for details on the keyboard interrupts. 3.3 PD6 -- IRQ2 The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt IRQ2 behaves similar to IRQ except it is edge-triggered only, and does not have wake-up function in STOP mode. See Section 5.2.2.2 for details on the external interrupt IRQ2. TPG 3-2 For More Information On This Product, Go to: www.freescale.com INPUT/OUTPUT PORTS MC68HC05SU3A Freescale Semiconductor, Inc. 3.4 Programmable Current Drive All I/O ports (except PB0 and PB1), when programmed as outputs, can source or sink a current of 10mA for driving LEDs directly. By setting the PIL bit in the Port Option Register (at $0A), PB5-PB7 can be programmed to a low-current mode that source or sink only a current of 2mA when programmed as output. This allows a direct drive to low current LEDs. 3 Note: Freescale Semiconductor, Inc... Although the ports each has high current drive capability, designs should limit the total port currents to not more than 100mA. 3.5 Programmable Pull-Up Devices Ports B, C, and D have 20K pull-up resistors, which can be connected or disconnected, by setting appropriate bits in the Port Option Register (at $0A). Port pins PB0 and PB1 each has a permanent 1.9K pull-up resistor connected. 3.5.1 Port Option Register Address bit 7 bit 6 bit 5 PIL bit 4 PDP bit 3 PCP bit 2 PBP bit 1 bit 0 State on reset 0000 0000 Port Option Register (POPR) $0A PIL -- PB5:PB7 current drive select 1 (set) - PB5-PB7 are configured to 2mA drive port. PB5-PB7 are configured to 10mA drive port. 0 (clear) - PDP -- Port D Pull-up 1 (set) - The internal 20K pull-up resistors are connected to the inputs of Port D. No pull-up resistor is connected to the inputs of Port D. 0 (clear) - PCP -- Port C Pull-up 1 (set) - The internal 20K pull-up resistors are connected to the inputs of Port C. No pull-up resistor is connected to the inputs of Port C. 0 (clear) - PBP -- PB2:PB7 Pull-up 1 (set) - The internal 20K pull-up resistors are connected to the inputs of PB2-PB7. No pull-up resistor is connected to the inputs of PB2-PB7. TPG 0 (clear) - MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com INPUT/OUTPUT PORTS 3-3 Freescale Semiconductor, Inc. 3 Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY TPG 3-4 For More Information On This Product, Go to: www.freescale.com INPUT/OUTPUT PORTS MC68HC05SU3A Freescale Semiconductor, Inc. 4 MEMORY AND REGISTERS The MC68HC05SU3A has 8K-bytes of addressable memory, consisting of I/O registers, user ROM, user RAM, and self-check ROM. Figure 4-1 shows the memory map for MC68HC05SU3A device. Freescale Semiconductor, Inc... 4 4.1 I/O Registers The I/O, status and control registers are located within the first 16 bytes of memory, from $0000 to $000F. These are shown in the memory map in Figure 4-1; and a summary of the register outline is shown in Table 4-1. Reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. 4.2 RAM The user RAM (including the stack) consists of 192 bytes. It is separated into two blocks at locations $0010 to $008F, and $00C0 to $00FF. The stack begins at address $00FF and proceeds down to $00C0. 4.3 ROM The user ROM consists of 3840 bytes of memory, from $1000 to $1EFF. Twelve bytes of user vectors are also available, from $1FF4 to $1FFF. Note: Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS 4-1 Freescale Semiconductor, Inc. 4.4 Memory Map Figure 4-1 shows the memory map for MC68HC05SU3A device. $0000 $000F $0010 I/O 16 Bytes Ports 8 Bytes User RAM 128 Bytes 0 Freescale Semiconductor, Inc... 4 $008F $0090 $00BF $00C0 Timer Registers 2 Bytes Port Option Register KBI Register Unused Misc. Register Reserved Reserved 2 Bytes Stack 64 Bytes 15 Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register Timer Data Register Timer Control Register Port Option Register Keyboard Interrupt Mask Register Miscellaneous Control Register Reserved Reserved Reserved $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $00FF $0100 Unused $0FFF $1000 User ROM 3840 Bytes $1EFF $1F00 Self-Check 240 Bytes $1FEF $1FF0 $1FFF User Vectors 12 Bytes $1FF0 $1FF2 $1FF4 $1FF6 $1FF8 $1FFA $1FFC $1FFE Reserved Reserved KBI Timer IRQ2 IRQ SWI RESET Figure 4-1 MC68HC05SU3A Memory Map TPG 4-2 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05SU3A Freescale Semiconductor, Inc. 4.5 I/O Registers Summary Table 4-1 shows a summary of I/O registers for MC68HC05SU3A device. Table 4-1 MC68HC05SU3A I/O Registers Freescale Semiconductor, Inc... Register Name Port A Data Port B Data Port C Data Port D Data Port A Data Direction Port B Data Direction Port C Data Direction Port D Data Direction Timer Data (TDR) Timer Control (TCR) Port Option (POPR) KBI Mask (KBIM) Miscellaneous Control (MCR) Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C bit 7 PA7 PB7 PC7 PD7 bit 6 PA6 PB6 PC6 PD6 bit 5 PA5 PB5 PC5 PD5 bit 4 PA4 PB4 PC4 PD4 bit 3 PA3 PB3 PC3 PD3 bit 2 PA2 PB2 PC2 PD2 bit 1 PA1 PB1 PC1 PD1 bit 0 PA0 PB0 PC0 PD0 State on reset unaffected unaffected unaffected unaffected 4 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0000 0000 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0000 0000 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0000 0000 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0000 0000 TD7 TIF TD6 TIM TD5 TCEX PIL KBE7 KBIE KBE6 KBIC KBE5 INTO TD4 TINE PDP KBE4 INTE TD3 PRER PCP KBE3 LVRE TD2 PR2 PBP KBE2 SM KBE1 TD1 PR1 TD0 PR0 1111 1111 0100 -000 --00 00-KBE0 0000 0000 IRQ2F IRQ2E 0001 0000 Reserved Reserved Reserved $0D $0E $0F TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS 4-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 4 THIS PAGE LEFT BLANK INTENTIONALLY TPG 4-4 For More Information On This Product, Go to: www.freescale.com MEMORY AND REGISTERS MC68HC05SU3A Freescale Semiconductor, Inc. 5 RESETS AND INTERRUPTS This section describes the reset and interrupt functions on the MCU. Freescale Semiconductor, Inc... 5 5.1 RESETS The MC68HC05SU3A can be reset in three ways: * * * by initial Power-On Reset function, (POR) by an active low input to the RESET pin, (RESET) by a Low Voltage Reset, (LVR) All of these resets will cause the program to go to the starting address, specified by the contents of memory locations $1FFE and $1FFF, and cause the interrupt mask (I-bit) of the Condition Code Register (CCR) to be set. 5.1.1 Power-On Reset (POR) The power-on reset (POR) occurs on power-up to allow the clock oscillator to stabilize. The POR is strictly for power-up conditions, and should not be used to detect any drops in power supply voltage. There is an oscillator stabilization delay of tPORL internal processor bus clock cycles after the oscillator becomes active. The RESET pin will be pulled down internally during these cycles. If the RESET pin is low (by external circuit) at the end of the tPORL period, the processor remains in the reset condition until RESET goes high. 5.1.2 RESET Pin The RESET input pin is used to reset the MCU to provide an orderly software start-up procedure. When using the external reset, the RESET pin must stay low for a minimum of 1.5tCYC. The RESET pin is connected to a Schmitt Trigger circuit as part of its input to improve noise immunity. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS 5-1 Freescale Semiconductor, Inc. 5.1.3 Low Voltage Reset (LVR) When the LVR function is enabled, an internal reset is generated if the supply voltage, VDD, drops below VLVR. (See Section 11 for value of VLVR). This LVR function is enabled by setting the LVRE bit in the Miscellaneous Control Register. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 KBIC bit 5 INTO bit 4 INTE bit 3 LVRE bit 2 SM bit 1 bit 0 State on reset Freescale Semiconductor, Inc... IRQ2F IRQ2E 0001 0000 5 LVRE -- Low Voltage Reset Enable 1 (set) - Low Voltage Reset function enabled. Low Voltage Reset function disabled. 0 (clear) - 5.2 INTERRUPTS The MC68HC05SU3A MCU can be interrupted by different sources - four maskable hardware interrupt and one non-maskable software interrupt: * * * * * Software Interrupt Instruction (SWI) External signal on IRQ pin External signal on IRQ2 pin TImer Overflow Keyboard If the interrupt mask bit (I-bit) in the Condition Code Register (CCR) is set, all maskable interrupts are disabled. Clearing the I-bit enables interrupts. Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Table 5-1 shows the relative priority of all the possible interrupt sources. Figure 5-2 shows the interrupt processing flow. TPG 5-2 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05SU3A Freescale Semiconductor, Inc. $00C0 (BOTTOM OF STACK) $00C1 UNSTACKING ORDER $00C2 * * * 5 4 3 2 1 1 2 3 4 5 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE) * * STACKING ORDER * * * * $00FD $00FE $00FF (TOP OF STACK) * * * Freescale Semiconductor, Inc... 5 Figure 5-1 Interrupt Stacking Order Table 5-1 Reset/Interrupt Vector Addresses Register -- -- -- -- TCR -- Flag Name -- -- -- -- TIF -- Interrupt Reset Software External Interrupt External Interrupt 2 Timer Overflow Keyboard CPU Interrupt RESET SWI IRQ IRQ2 TIF KBI Vector Address $1FFE-$1FFF $1FFC-$1FFD $1FFA-$1FFB $1FF8-$1FF9 $1FF6-$1FF7 $1FF4-$1FF5 Priority highest lowest 5.2.1 Non-maskable Software Interrupt (SWI) The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS 5-3 Freescale Semiconductor, Inc. From RESET Y Is I-bit Set? N IRQ External Interrupt ? N IRQ2 External Interrupt ? N Y Y PC (SP, SP-1) X (SP-2) A (SP-3) CC (SP-4) Y Clear External Interrupt Request Latch Freescale Semiconductor, Inc... 5 Timer Interrupt? N Set I-bit in CCR Keyboard Interrupt? N Y Load Interrupt Vectors to Program Counter Fetch Next Instruction SWI Instruction? N Y RTI Instruction? N Execute Instruction Y Restore Registers from Stack CC, A, X, PC Figure 5-2 Hardware Interrupt Processing Flowchart TPG 5-4 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05SU3A Freescale Semiconductor, Inc. 5.2.2 Maskable Hardware Interrupts If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the I-bit allows interrupt processing to occur. Note: Freescale Semiconductor, Inc... The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared. 5.2.2.1 External Interrupt (IRQ) The external interrupt IRQ is controlled by two bits in the Miscellaneous Control Register ($0C). Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 KBIC bit 5 INTO bit 4 INTE bit 3 LVRE bit 2 SM bit 1 bit 0 State on reset 5 IRQ2F IRQ2E 0001 0000 INTE -- INTerrupt Enable 1 (set) - External interrupt IRQ is enabled. External interrupt is disabled. 0 (clear) - The external IRQ is default enabled at power-on reset. INTO -- INTerrupt Option 1 (set) - Negative-edge sensitive triggering for IRQ. Negative-level sensitive triggering for IRQ. 0 (clear) - When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. When the interrupt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the Condition Code Register is set. This masks further interrupts until the present one is serviced. The service routine address is specified by the contents in $1FFA-$1FFB. The interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are spaced far enough apart to be serviced. The minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The second configuration shows several interrupt lines wired-OR to perform the interrupt at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS 5-5 Freescale Semiconductor, Inc. INTO BIT VDD VDD D Q & + & & I-BIT (CCR) 100K IRQ C R Q EXTERNAL INTERRUPT REQUEST Freescale Semiconductor, Inc... 5 POWER-ON RESET + EXTERNAL RESET EXTERNAL INTERRUPT BEING SERVICED (IRQ ONLY) (a) Interrupt Function Diagram IRQ tILIH tILIL EDGE SENSITIVE TRIGGER CONDITION The minimum pulse width tILIH is either 125ns (VDD=5V) or 250ns (VDD=3V). The period tILIL should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 21 tCYC cycles. tILIH LEVEL SENSITIVE TRIGGER CONDITION if after servicing an interrupt the external interrupt pin (IRQ) remains low, then the next interrupt is recognized. Normally used with pull-up resistors for wired-OR connection. Wired ORed Interrupt signals IRQ (b) Interrupt Mode Diagram Figure 5-3 External Interrupt TPG 5-6 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05SU3A Freescale Semiconductor, Inc. 5.2.2.2 External Interrupt 2 (IRQ2) The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt IRQ2 behaves similar to IRQ except it is edge-triggered only, and does not have wake-up function in STOP mode. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 KBIC bit 5 INTO bit 4 INTE bit 3 LVRE bit 2 SM bit 1 bit 0 State on reset Freescale Semiconductor, Inc... IRQ2F IRQ2E 0001 0000 IRQ2E -- IRQ2 Enable 1 (set) - External interrupt IRQ2 is enabled. External interrupt IRQ2 is disabled. 5 0 (clear) - IRQ2F -- IRQ2 Flag clear This is a write-only bit and always read as "0". 1 (set) - Writing a "1" clears the IRQ2 interrupt latch. Writing a "0" has no effect. 0 (clear) - When a negative-edge is sensed on IRQ2 pin, an external interrupt occurs. The actual processor interrupt is generated only if the I-bit in the CCR is also cleared. When the interrupt is recognized, the current state of the processor is pushed onto the stack and the I-bit in the CCR is set. This masks further interrupts until the present one is serviced. The latch for IRQ2 is cleared by reset or by writing a "1" to the IRQ2F bit in the MCR in the interrupt service routine. The interrupt service routine address is specified by the contents in $1FF8-$1FF9. 5.2.2.3 Timer Interrupt The timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. The interrupt enable and flag for the timer interrupt are located in the Timer Control Register. Address bit 7 Timer Control Register (TCR) $09 TIF bit 6 TIM bit 5 TCEX bit 4 TINE bit 3 PREP bit 2 PR2 bit 1 PR1 bit 0 PR0 State on reset 0100 -100 TIM -- Timer Interrupt Mask 1 (set) - Timer interrupt is disabled. Timer interrupt is enabled. 0 (clear) - TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS 5-7 Freescale Semiconductor, Inc. TIF -- Timer Interrupt Flag 1 (set) - A timer interrupt (timer overflow) has occurred. A timer interrupt (timer overflow) has not occurred. 0 (clear) - The I-bit in the CCR must be cleared in order for the timer interrupt to be processed. The interrupt will vector to the interrupt service routine at the address specified by the contents in $1FF6-$1FF7. Freescale Semiconductor, Inc... 5.2.2.4 Keyboard Interrupt (KBI) 5 Keyboard interrupt function is associated with Port A pins. The keyboard interrupt function is enabled by setting the keyboard interrupt enable bit KBIE (bit 7 of MCR at $0C) and the individual enable bits KBE0-KBE7 (bits 0-7 of KBIM at $0B). When the KBEx bit is set, the corresponding Port A pin will be configured as an input pin, regardless of the DDR setting, and a 20K pull-up resistor is connected to the pin, as shown in Figure 5-4. When a high to low transition is sensed on the pin, a keyboard interrupt will be generated. An interrupt to the CPU will be generated if the I-bit in the CCR is cleared. The keyboard interrupt flag should be cleared in the interrupt service routine (by writing a "1" to KBIC bit in the MCR at $0C) after the key is debounced. Debouncing will avoid spurious false triggering. The keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is specified by the contents in $1FF4-$1FF5. KBEx of KBIM VDD & & Keyboard Interrupt request & & KBIE bit of MCR ($0C bit 7) 20K 1 input for each of PA0-PA7 (8 input NAND) & DDR0-DDR7 Internal Data bit (0-7), Port A Pad Logic PAx Figure 5-4 Keyboard Interrupt Circuitry TPG 5-8 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05SU3A Freescale Semiconductor, Inc. The KBIE bit in the Miscellaneous Control Register controls the master enable for the keyboard interrupts. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 KBIC bit 5 INTO bit 4 INTE bit 3 LVRE bit 2 SM bit 1 bit 0 State on reset IRQ2F IRQ2E 0001 0000 KBIE -- KeyBoard Interrupt Enable 1 (set) - Keyboard interrupts master enabled. Keyboard interrupts master disabled. Freescale Semiconductor, Inc... 0 (clear) - KBIC -- KeyBoard Interrupt Clear This is a write-only bit and always read as "0". 1 (set) - Writing a "1" clears the keyboard interrupt latch. Writing a "0" has no effect. 5 0 (clear) - The Keyboard Interrupt Mask Register (KBIMR) masks individual keyboard interrupt pins and setting of the internal pull-up resistors on port A. Address bit 7 KBIMR $0B KBE7 bit 6 KBE6 bit 5 KBE5 bit 4 KBE4 bit 3 KBE3 bit 2 KBE2 bit 1 KBE1 bit 0 State on reset KBE0 0000 0000 KBEx -- PAx Keyboard Interrupt Enable 1 (set) - Keyboard interrupt enabled for PAx. A 20K internal pull-up resistor is connected. High to low transition on PAx will cause a keyboard interrupt. Keyboard interrupt for PAx pin is masked. Any transitions on PAx will not set any flags. 0 (clear) - TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS 5-9 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 5 THIS PAGE LEFT BLANK INTENTIONALLY TPG 5-10 For More Information On This Product, Go to: www.freescale.com RESETS AND INTERRUPTS MC68HC05SU3A Freescale Semiconductor, Inc. 6 TIMER This section describes the operation of the 8-bit count-down timer in the MC68HC05SU3A. Freescale Semiconductor, Inc... 6.1 Timer Overview 6 The MC68HC05SU3A timer block diagram is shown in Figure 6-1. The timer contains a single 8-bit software programmable count-down counter with a 7-bit software selectable prescaler. The counter may be preset under software control and decrements towards zero. When the counter decrements to zero, the timer interrupt flag (TIF bit in Timer Control Register, TCR) is set. Once timer interrupt flag is set, an interrupt is generated to the CPU only if the TIM bit in the TCR and I-bit in the CCR are cleared. When a interrupt is recognized, after completion of the current instruction, the processor proceeds to store the appropriate registers on the stack and then fetches the timer interrupt vector from locations $1FF6 and $1FF7. The counter continues to count after it reaches zero, allowing the software to determine the number of internal or external clocks since the timer interrupt flag was set. The counter may be read at any time by the processor without disturbing the count. The contents of the counter become stable prior to the read portion of a cycle and do not change during the read. The timer interrupt flag remains set until cleared by the software. If a write occurs before the timer interrupt is served, the interrupt is lost. The timer interrupt flag may also be used as a scanned status bit in a non-interrupt mode of operation. The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit 0, 1, 2 (PR0, PR1, PR2) of TCR are programmed to choose the appropriate prescaler output which is used as the 8-bit counter clock input. The processor cannot write into or read from the prescaler; however, its contents can be cleared to all zeros by writing to the PRER bit in the TCR. This will allow for truncation-free counting. The input clock for the timer sub-system is selectable from internal, external, or a combination of internal and external sources. The TCEX and TINE bits in the Timer Control Register selects the timer input clock. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com TIMER 6-1 Freescale Semiconductor, Inc. 8 Timer Data Register ($08) Freescale Semiconductor, Inc... 8 8-bit count-down timer counter 7-bit prescaler counter RST Internal Bus 6 8 Prescaler Select Logic (8 to 1 MUX) Overflow Detect Circuit Interrupt Circuit 8 TIF TIM TCEX TINE PRER PR2 PR1 PR0 Timer Control Register ($09) Clock Source Logic TIMER Internal Processor Clock TCEX 0 0 1 1 TINE 0 1 0 1 Clock Source Internal clock to timer "AND" of internal clock and TIMER pin to timer Input clock to timer disabled TIMER pin to timer Figure 6-1 Timer Block Diagram TPG 6-2 For More Information On This Product, Go to: www.freescale.com TIMER MC68HC05SU3A Freescale Semiconductor, Inc. 6.2 Timer Control Register (TCR) The TCR enables the software to control the operation of the timer. Address $09 bit 7 TIF bit 6 TIM bit 5 TCEX bit 4 TINE bit 3 PRER bit 2 PRE2 bit 1 PRE1 bit 0 PRE0 State on reset 0100 -100 Freescale Semiconductor, Inc... TIF -- Timer Interrupt Flag 1 (set) - The timer has reached a count of zero. The timer has not reached a count of zero. 0 (clear) - The timer interrupt flag is set when the 8-bit counter decrements to zero. This bit is cleared on reset, or by writing a "0" to the TIF bit. TIM -- Timer Interrupt Mask 1 (set) - Timer interrupt request to the CPU is masked (disabled). Timer interrupt request to the CPU is not masked (enabled). 6 0 (clear) - A reset sets this bit to one; it must then be cleared by software to enable the timer interrupt to the CPU. This timer interrupt mask only masks timer interrupt request to the CPU, and does not affect counting of the 8-bit counter or the setting of TIF. TCEX -- Timer Clock EXternal TINE -- Timer INput Enable These two bits selects the source of the timer clock. Reset or power-on clears these bits to zero. TCEX 0 0 1 1 TINE 0 1 0 1 Clock Source Internal clock to timer "AND" of internal clock and TIMER pin to timer Input clock to timer disabled TIMER pin to timer PRER -- PREscaler Reset Writing a "1" to this write-only bit will reset the prescaler to zero, which is necessary for any new counts set by writing to the Timer Data Register.This bit always reads as zero, and is not affected by reset. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com TIMER 6-3 Freescale Semiconductor, Inc. PR2:PR0 These three bits enable the program to select the division ratio of the prescaler. On reset, these three bits are set to "100", which corresponds to a division ratio of 16. Freescale Semiconductor, Inc... PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Divide Ratio 1 2 4 8 16 32 64 128 6 6.3 Timer Data Register (TDR) The TDR is a read/write register which contains the current value of the 8-bit count-down timer counter when read. Reading this register does not disturb the counter operation. Address $08 bit 7 TD7 bit 6 TD6 bit 5 TD5 bit 4 TD4 bit 3 TD3 bit 2 TD2 bit 1 TD1 bit 0 TD0 State on reset 1111 1111 6.4 Operation during Low Power Modes The timer ceases counting in STOP mode. When STOP mode is exited by an external interrupt (IRQ or KBI), the internal oscillator will resume its operation, followed by internal processor stabilization delay. The timer is then cleared to zero and resumes its operation. The TIF bit in the TCR will be set. To avoid generating a timer interrupt when exiting STOP mode, it is recommended to set the TIM bit prior entering STOP mode. After exiting STOP mode TIF bit can then be cleared. The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. TPG 6-4 For More Information On This Product, Go to: www.freescale.com TIMER MC68HC05SU3A Freescale Semiconductor, Inc. 7 CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05SU3A. Freescale Semiconductor, Inc... 7.1 Registers The MCU contains five registers, as shown in the programming model of Figure 7-1. The interrupt stacking order is shown in Figure 7-2. 7 7 15 7 0 Accumulator 0 Index register 0 Program counter 15 7 0 0000000011 7 0 111HINZC Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry 7 Figure 7-1 Programming model 7.1.1 Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-1 Freescale Semiconductor, Inc. 7 Increasing memory address Condition code register Accumulator Index register Program counter high Program counter low Return 0 Stack Interrupt Decreasing memory address Unstack Figure 7-2 Stacking order Freescale Semiconductor, Inc... 7.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. 7.1.3 Program counter (PC) 7 The program counter is a 16-bit register, which contains the address of the next byte to be fetched. 7.1.4 Stack pointer (SP) The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 7.1.5 Condition code register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. TPG 7-2 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05SU3A Freescale Semiconductor, Inc. Interrupt (I) When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. Freescale Semiconductor, Inc... 7 7.2 Instruction set The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: - - - - - Register/memory Read/modify/write Branch Bit manipulation Control The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 7-1. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-3 Freescale Semiconductor, Inc. 7.2.1 Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 7-2 for a complete list of register/memory instructions. Freescale Semiconductor, Inc... 7.2.2 Branch instructions These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 7-3. 7.2.3 Bit manipulation instructions 7 The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 7-4. 7.2.4 Read/modify/write instructions These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 7-5 for a complete list of read/modify/write instructions. 7.2.5 Control instructions These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 7-6 for a complete list of control instructions. 7.2.6 Tables Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 7-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 7-8). TPG 7-4 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05SU3A Freescale Semiconductor, Inc. Table 7-1 MUL instruction X:A X*A Multiplies the eight bits in the index register by the eight Description bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. H : Cleared I : Not affected Condition N : Not affected codes Z : Not affected C : Cleared Source MUL Addressing mode Cycles Bytes Opcode Form Inherent 11 1 $42 Operation Freescale Semiconductor, Inc... Table 7-2 Register/memory instructions Addressing modes Immediate Mnemonic Direct Extended Indexed (no offset) # Cycles Opcode Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes Indexed (16-bit offset) # Cycles # Bytes 7 5 5 6 6 5 5 5 5 5 5 5 5 5 5 4 7 # Cycles # Cycles Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with borrow AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR A6 AE 2 2 2 2 B6 BE B7 BF 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5 C6 CE C7 CF CB C9 C0 C2 C4 CA C8 C1 C3 C5 CC CD 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 # Cycles 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6 Opcode Opcode Opcode # Bytes # Bytes # Bytes F6 FE F7 FF FB F9 F0 F2 F4 FA F8 F1 F3 F5 FC FD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5 E6 EE E7 EF EB E9 E0 E2 E4 EA E8 E1 E3 E5 EC ED 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6 D6 DE D7 DF DB D9 D0 D2 D4 DA D8 D1 D3 D5 DC DD 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 AB A9 A0 A2 A4 AA A8 A1 A3 A5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BB B9 B0 B2 B4 BA B8 B1 B3 B5 BC BD TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-5 Freescale Semiconductor, Inc. Table 7-3 Branch instructions Relative addressing mode Opcode # Bytes # Cycles 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 24 2 3 25 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 2A 2 3 2B 2 3 2C 2 3 2D 2 3 2E 2 3 2F 2 3 AD 2 6 Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine Freescale Semiconductor, Inc... 7 Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Table 7-4 Bit manipulation instructions Addressing modes Bit set/clear Bit test and branch Opcode # Bytes # Cycles Opcode # Bytes # Cycles 2*n 3 5 01+2*n 3 5 10+2*n 2 5 11+2*n 2 5 Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n Mnemonic BRSET n (n=0-7) BRCLR n (n=0-7) BSET n (n=0-7) BCLR n (n=0-7) TPG 7-6 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05SU3A Freescale Semiconductor, Inc. Table 7-5 Read/modify/write instructions Addressing modes Inherent (A) Mnemonic # Cycles Opcode Inherent (X) # Cycles Opcode Opcode Direct Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles 6 6 6 6 6 6 6 6 6 6 5 Opcode 6C 6A 6F 63 60 69 66 68 64 67 6D # Bytes 2 2 2 2 2 2 2 2 2 2 2 # Bytes # Bytes Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Multiply Freescale Semiconductor, Inc... INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL 4C 4A 4F 43 40 49 46 48 44 47 4D 42 1 1 1 1 1 1 1 1 1 1 1 1 3 5C 3 5A 3 5F 3 53 3 50 3 59 3 56 3 58 3 54 3 57 3 5D 11 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3C 3A 3F 33 30 39 36 38 34 37 3D # Bytes 2 2 2 2 2 2 2 2 2 2 2 5 5 5 5 5 5 5 5 5 5 4 7C 7A 7F 73 70 79 76 78 74 77 7D 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5 5 5 5 5 5 5 4 7 Table 7-6 Control instructions Inherent addressing mode Opcode # Bytes # Cycles 97 1 2 9F 1 2 99 1 2 98 1 2 9B 1 2 9A 1 2 83 1 10 81 1 6 80 1 9 9C 1 2 9D 1 2 8E 1 2 8F 1 2 Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-7 Freescale Semiconductor, Inc. Table 7-7 Instruction set Addressing modes EXT REL IX IX1 Condition codes I NZ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * 0 * 1 Mnemonic ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP INH IMM DIR IX2 BSC BTB Freescale Semiconductor, Inc... 7 H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * * * * * * * * * * * * * * * * * * * * * * * 0 * * Address mode abbreviations BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative I N Z C Not implemented H Condition code symbols Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set TPG 7-8 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05SU3A Freescale Semiconductor, Inc. Table 7-7 Instruction set (Continued) Addressing modes EXT REL IX IX1 Condition codes I NZ * * * * * * * * * * * * * * * 0 * * * * * * * * * * * * * ??? * * * * * * * 1 * * * 0 * * * * 1 * * * * * * * 0 * * * * Mnemonic COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT INH IMM DIR IX2 BSC BTB Freescale Semiconductor, Inc... H * * * * * * * * * * * 0 * * * * * * ? * * * * * * * * * * * * * C 1 * * * * * * * 0 * * * ? * 1 * * * * * * * * * 7 Address mode abbreviations BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative I N Z C Not implemented H Condition code symbols Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-9 Freescale Semiconductor, Inc... 7 7-10 Control High 3 IX 3 High 3 Low NEG NEGA NEGX NEG SUB SUB SUB SUB CMP SBC CPX AND BIT LDA STA EXT 3 4 EXT 3 4 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 5 3 3 6 Bit manipulation BTB BSC 0 1 0000 0001 DIR 3 0011 IX 7 0111 DIR B 1011 IX F 1111 4 2 3 4 5 Branch REL 2 0010 INH 4 0100 INH 8 1000 INH 9 1001 IMM A 1010 IX1 E 1110 SUB SUB CMP SBC CPX IX1 1 4 IX1 1 4 IX1 1 4 2 IMM 2 2 DIR 3 3 EXT 3 4 9 INH 6 5 Read/modify/write INH IX1 5 6 0101 0110 Register/memory EXT IX2 C D 1100 1101 NEG RTI RTS CMP CMP SBC CPX AND BIT LDA STA EOR ADC DIR 3 3 DIR 3 3 EXT 3 5 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 IX 1 INH 1 INH 2 IX1 1 BRSET0 REL 2 3 DIR 1 5 BSET0 CMP CMP SBC CPX AND BIT IX2 2 5 IX1 1 4 IX1 1 4 2 1 INH 5 BRA 3 BRCLR0 REL 3 BTB 2 5 BCLR0 MUL SBC CPX AND BIT LDA STA 2 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 1 2 11 BSC 2 5 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 DIR 3 3 IX 3 BRN SBC COMX COM CPX 2 3 6 3 BRSET1 REL 3 BTB 2 5 BSET1 COM COMA SWI INH 5 INH 3 BSC 2 5 BHI COM LSR AND 2 IX IX 1 5 5 10 REL 2 3 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 IX1 1 3 BRCLR1 LSR LSRA LSRX LSR BIT 2 INH 2 INH 1 DIR 1 REL 2 3 REL 3 BTB 2 5 BCLR1 BSC 2 5 BLS IX 3 IX 3 3 BRSET2 BTB 2 5 BSET2 BSC 2 5 BCC AND BIT LDA IX1 1 4 3 BRCLR2 ROR RORA RORX ROR LDA 2 5 3 3 6 BTB 2 5 BCLR2 ROR ASR TAX 1 IX 5 2 INH 2 5 REL 2 3 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 BSC 2 5 BCS IX 3 IX 3 3 BRSET3 ASR ASRA ASRX ASR LSL CLC EOR EOR ADC ORA ADD IMM 2 DIR 3 3 1 IX1 1 6 BTB 2 5 BSET3 BSC 2 5 BNE LDA IX2 2 6 3 BRCLR3 REL 2 3 BTB 2 5 BCLR3 LSL LSLA LSLX ROLX ROL SEC ADC ORA ADD IMM 2 2 IMM 2 2 1 INH 2 3 IX1 1 6 DIR 1 5 INH 2 3 INH 1 3 BSC 2 5 BEQ LSL ROL DEC CLI 1 IX IX 5 INH 2 2 INH 2 2 INH 2 INH 2 INH 2 2 IX 5 INH 2 2 IMM 2 2 IX 5 2 DIR 3 3 REL 2 3 DIR 1 5 INH 1 3 INH 1 3 INH 2 3 IX1 1 6 IX1 1 STA EOR ADC EXT 3 4 IX2 2 5 IX2 2 5 IX2 2 5 IX1 1 5 IX1 1 4 STA EOR ADC EOR IX1 1 4 IX1 1 4 IX 4 IX 3 IX 3 3 BRSET4 ROL ROLA DECA DECX DEC SEI 1 INH 2 INH 1 REL 2 3 DIR 1 5 DIR 1 BTB 2 5 BSET4 BSC 2 5 BHCC 3 BRCLR4 DEC REL 2 3 REL 3 BTB 2 5 BCLR4 BSC 2 5 BHCS ADC ORA ADD DIR 3 2 3 BRSET5 BTB 2 5 BSET5 BSC 2 5 BPL ORA EXT 3 4 EXT 3 3 ORA ADD JMP JMP JMP IX2 2 5 IX2 2 4 ORA ADD JMP IX1 1 4 IX 3 IX 3 3 BRCLR5 INC INCA INCX INC RSP 1 5 3 3 6 BTB 2 5 BCLR5 INC TST NOP 1 IX IX 4 5 BSC 2 5 BMI ADD IX1 1 3 2 3 BRSET6 REL 2 3 BTB 2 5 BSET6 TST TSTA TSTX TST IX1 1 INH 2 INH 1 DIR 1 DIR 1 4 INH 2 3 IX1 1 5 INH 1 3 BSC 2 5 BMC JMP BSR LDX 6 IX 2 DIR 3 5 EXT 3 6 IX2 2 7 IX1 1 6 IX 5 3 BRCLR6 REL 2 3 BTB 2 5 BCLR6 STOP 1 2 REL 3 BSC 2 5 BMS JSR REL 2 2 2 IMM 2 JSR LDX DIR 3 3 DIR 3 4 JSR LDX EXT 3 4 EXT 3 5 JSR LDX IX2 2 5 IX2 2 6 JSR LDX IX1 1 4 3 Table 7-8 M68HC05 opcode map BRSET7 CLR CLRA CLRX CLR IX1 1 IX 1 INH 2 5 3 3 6 BTB 2 5 BSET7 CLR WAIT 5 INH 2 INH 1 REL 2 DIR 1 INH 1 BSC 2 5 BIL LDX TXA 2 INH 2 IX 3 IX1 1 5 IX 4 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com STX STX DIR 3 CPU CORE AND INSTRUCTION SET STX EXT 3 IX2 2 3 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 STX STX IX1 1 IX BRCLR7 BTB 2 5 BCLR7 BSC 2 5 BIH 3 BTB 2 BSC 2 Low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 Abbreviations for address modes and registers Legend F 1111 Mnemonic 1 Opcode in hexadecimal Opcode in binary SUB Not implemented Bytes Cycles Address mode 3 IX BSC BTB DIR EXT INH IMM IX IX1 IX2 REL A X Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accumulator Index register Bit set/clear Bit test and branch Direct Extended Inherent Immediate MC68HC05SU3A 0 0000 TPG Freescale Semiconductor, Inc. 7.3 Addressing modes Freescale Semiconductor, Inc... Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide. 7.3.1 Inherent 7 In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long. 7.3.2 Immediate In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC PC+2 7.3.3 Direct In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-11 Freescale Semiconductor, Inc. 7.3.4 Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2) Freescale Semiconductor, Inc... 7.3.5 Indexed, no offset In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X 7 7.3.6 Indexed, 8-bit offset In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1) 7.3.7 Indexed, 16-bit offset In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2) TPG 7-12 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05SU3A Freescale Semiconductor, Inc. 7.3.8 Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2 Freescale Semiconductor, Inc... 7.3.9 Bit set/clear In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) 7 7.3.10 Bit test and branch The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET 7-13 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 7 THIS PAGE LEFT BLANK INTENTIONALLY TPG 7-14 For More Information On This Product, Go to: www.freescale.com CPU CORE AND INSTRUCTION SET MC68HC05SU3A Freescale Semiconductor, Inc. 8 LOW POWER MODES The MC68HC05SU3A has three low-power operating modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The flow of the STOP and WAIT modes is shown in Figure 8-1. The third low-power operating mode is the SLOW mode. Freescale Semiconductor, Inc... 8.1 STOP Mode Execution of the STOP instruction places the MCU in its lowest power consumption mode. In the STOP mode the internal oscillator is turned off, halting all internal processing. When the CPU enters STOP mode the I-bit in the Condition Code Register is cleared automatically, so that hardware interrupts, IRQ and KBI can "wake" the MCU. All other registers and memory contents remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the STOP mode only by a hardware interrupt or an externally generated reset. When exiting the STOP mode the internal oscillator will resume after a pre-defined number of internal processor clock cycles, due to oscillator stabilization. 8 8.2 WAIT Mode The WAIT instruction places the MCU in a low-power mode, but consumes more power than the STOP mode. In the WAIT mode the internal processor clock is halted, suspending all processor and internal bus activities. Other Internal clocks remain active, permitting interrupts to be generated from the Timer. The Timer may be used to generate a periodic exit from the WAIT mode or, in conjunction with the external Timer pin, on the occurrence of external events. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any hardware interrupt can "wake" the MCU. All other registers, memory, and input/output lines remain in their previous states. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com LOW POWER MODES 8-1 Freescale Semiconductor, Inc. STOP WAIT Stop External Oscillator, Stop Internal Timer Clock, and Reset Start-Up Delay External Oscillator Active, and Internal Timer Clock Active Freescale Semiconductor, Inc... Stop Internal Processor Clock, Clear I-Bit in CCR Stop Internal Processor Clock, Clear I-Bit in CCR External RESET? N Y Y External RESET? N N IRQ or KBI Interrupt? Y Reset External Oscillator, and Stabilization Delay Y External Hardware Interrupt? N 8 N End of Start-Up Delay? Y Y Timer Interrupt? N Restart Internal Processor Clock Y Keyboard Interrupt? N Fetch Reset Vector or Service Interrupt (a) Stack (b) Set I-Bit (c) Vector to Interrupt Routine Figure 8-1 STOP and WAIT Mode Flowcharts TPG 8-2 For More Information On This Product, Go to: www.freescale.com LOW POWER MODES MC68HC05SU3A Freescale Semiconductor, Inc. 8.3 SLOW Mode The SLOW mode function is controlled by the SM bit in the Miscellaneous Control Register. When the SM bit is set, the internal bus clock is divided by 16, resulting to a frequency equal to the oscillator frequency divide by 32. This feature permits a slow down of all the internal operations and thus reduces power consumption -- particularly useful while in WAIT mode. The SM bit is automatically cleared while going to STOP mode. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 KBIC bit 5 INTO bit 4 INTE bit 3 LVRE bit 2 SM bit 1 bit 0 State on reset Freescale Semiconductor, Inc... IRQ2F IRQ2E 0001 0000 SM -- Slow Mode 1 (set) - Slow mode enabled. Internal bus frequency fOP =fOSC / 32. Slow mode disabled. Internal bus frequency fOP =fOSC / 2. 0 (clear) - 8 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com LOW POWER MODES 8-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 8 THIS PAGE LEFT BLANK INTENTIONALLY TPG 8-4 For More Information On This Product, Go to: www.freescale.com LOW POWER MODES MC68HC05SU3A Freescale Semiconductor, Inc. 9 OPERATING MODES The MC68HC05SU3A has two modes of operation: the User Mode and the Self-Check Mode. Table 9-1 shows the conditions required for entering the two operating modes. Table 9-1 Mode Selection RESET 5V Freescale Semiconductor, Inc... VPP VSS to VDD VTST PB1 VSS to VDD VDD MODE USER SELF-CHECK VTST =2xVDD 9.1 User Mode The normal operating mode of the MC68HC05SU3A is the User mode. This mode is entered on the rising edge of RESET when the VPP and PB1 pins are between VSS and VDD. 9 9.2 Self-Check Mode The Self-check mode is provided on the MC68HC05SU3A for the user to check device functions with an on-chip self-check program masked at location $1F00 to $1FEF under minimum hardware support. The self-check schematic is shown in Figure 9-1. Self-check mode is entered on the rising edge of RESET when the VPP pin is at VTST (2xVDD) and PB1 pin is at VDD. Once in the self-check mode, PB1 can then be used for other purposes. After entering the self-check mode, CPU branches to the self-check program and carries out the self-check. Self-check is a repetitive test, i.e. if all parts are checked to be good, the CPU will repeat the self-check again. Therefore, the LEDs attached to Port A will be flashing if the device is good; else the combination of LEDs' on-off pattern can show what part of the device is suspected to be bad. Table 9-2 lists the LEDs' on-off patterns and their corresponding indications. TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com OPERATING MODES 9-1 Freescale Semiconductor, Inc. MC68HC05SU3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2 PD3 PD4 PD5 PD6/IRQ2 PD7 RESET 1F + +5V PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 IRQ TIMER Freescale Semiconductor, Inc... OUT Crystal OSC +5V 4MHz OSC1 OSC2 4K7 RESET 10K +5V 330 D1 PB0 PB4 330 D2 PB1 PB5 330 D3 PB2 PB6 330 D4 PB3 PB7 9 VPP VPP VDD VSS 0.1F +5V + 47F Figure 9-1 MC68HC05SU3A Self-Check Circuit TPG 9-2 For More Information On This Product, Go to: www.freescale.com OPERATING MODES MC68HC05SU3A Freescale Semiconductor, Inc. Table 9-2 Self-Check Report D3 D2 Flashing 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1=LED on, 0=LED off D4 D1 1 0 1 0 1 0 0 1 REMARKS O.K. (self-check is on-going) Bad port A Bad port B Bad port C Bad port D Bad RAM Bad ROM Bad SWI Bad IRQ Freescale Semiconductor, Inc... 9 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com OPERATING MODES 9-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY 9 TPG 9-4 For More Information On This Product, Go to: www.freescale.com OPERATING MODES MC68HC05SU3A Freescale Semiconductor, Inc. 10 ELECTRICAL SPECIFICATIONS This section contains the electrical specifications for MC68HC05SU3A. Freescale Semiconductor, Inc... 10.1 Maximum Ratings (Voltages referenced to VSS) RATINGS Supply Voltage Input Voltage VPP Pin Current Drain per pin excluding VDD and VSS Operating Temperature Standard Extended Storage Temperature Range SYMBOL VDD VIN VIN ID TA TSTG VALUE -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to 2xVDD +0.3 25 TL to TH 0 to +70 -40 to +85 -65 to +150 UNIT V V V mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout)VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD). 10 10.2 Thermal Characteristics CHARACTERISTICS Thermal resistance DIP SOIC QFP SYMBOL JA JA JA VALUE 60 60 60 UNIT C/W C/W C/W TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS 10-1 Freescale Semiconductor, Inc. 10.3 DC Electrical Characteristics Table 10-1 DC Electrical Characteristics (VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) CHARACTERISTICS SYMBOL Output voltage ILOAD = -10A VOH ILOAD = +10A VOL Output high voltage (ILOAD =-0.8mA): All Ports VOH Output low voltage (ILOAD =+1.6mA): All Ports VOL Output high current (VOH =2.5V) All ports IOH (VOH =2.0V) PB5-PB7 in low-current mode (25C) (VOH =2.0V) PB5-PB7 in low-current mode (0 to 70C) Output low current (VOL =2.5V) All ports, except PB0 and PB1 (VOL =3.0V) PB5-PB7 in low-current mode IOL (VOL =2.5V) PB0, PB1 (VOL =0.4V) PB0, PB1 Total I/O port current IPORT Either source or sink Input high voltage VIH PA0-PA7, PB0, PB1, IRQ, RESET, OSC1 Input low voltage VIL PA0-PA7, PB0, PB1, IRQ, RESET, OSC1 Supply current: Run Wait IDD Stop 25C 0C to +70C (Standard) I/O ports high-Z leakage current IIL PA0-PA7, PB2-PB7, PC0-PC7, PD0-PD7 Input current IIN IRQ, OSC1 Capacitance Ports (as input or output) COUT RESET, IRQ, OSC1, OSC2 CIN Low voltage reset threshold VLVR Pull-up resistor PA0-PA7, PB2-PB7, PC0-PC7, PD0-PD7 PB0, PB1 RESET IRQ MINIMUM VDD -0.1 -- VDD -0.8 -- 7 1.5 1.25 7 2 40 10 -- 0.7xVDD VSS -- -- -- -- -- -- -- -- 2.8 15 1.6 20 60 TYPICAL -- -- -- -- 10 1.75 1.75 10 3.5 70 20 100 -- -- 5.0 1.3 8 10 -- -- -- -- 3.5 20 1.9 60 100 MAXIMUM -- 0.1 -- 0.4 30 5 5 30 4.8 -- -- -- VDD 0.2xVDD 7.5 2.0 20 30 10 2 12 8 4.2 90 2.9 150 300 UNIT V V V V mA mA mA mA mA mA mA mA V V mA mA A A A A pF pF V K K K K Freescale Semiconductor, Inc... 10 RPU Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25C only. (3) Wait IDD: Only timer system active. (4) Wait, Stop IDD: All ports configured as inputs, VIL=0.2Vdc, VIH=VDD-0.2Vdc. (5) Run (operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (f OSC =2.0MHz), all inputs 0.2Vdc from rail; no DC loads, less than 50pF on all outputs, CL=20pF on OSC2. (6) Stop IDD measured with OSC1=VSS. (7) Wait IDD is affected linearly by the OSC2 capacitance. TPG 10-2 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05SU3A Freescale Semiconductor, Inc. 10.4 Control Timing Table 10-2 Control Timing (VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) CHARACTERISTICS SYMBOL Frequency of operation RC oscillator Option fOSC Crystal option External clock option Internal operating frequency (fOSC/2) RC oscillator fOP Crystal External clock Processor cycle time (1/fOP) tCYC RC oscillator stabilization time tRCON Crystal oscillator start-up time (crystal oscillator) tOXOV Stop recovery start-up time (crystal oscillator) tILCH RESET pulse width low tRL Timer resolution(2) tRESL Interrupt pulse width low (edge-triggered) tILIH Interrupt pulse period tILIL PA0-PA7 interrupt pulse width high (edge-triggered) tIHIL PA0-PA7 interrupt pulse period tIHIH OSC1 pulse width t RC oscillator frequency combined stability(4) fOSC=2.0MHz, VDD=5.0Vdc10%, tA =-40C to +85C fOSC fOSC fOSC=2.0MHz, VDD=5.0Vdc10%, tA =0C to +40C Notes: (1) VDD=5.0Vdc10%, VSS=0Vdc, tA=tL to tH (2) The TIMER input pin is the limiting factor in determining timer resolution. (3) The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t CYC. (4) Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C). MINIMUM 0.1 0.1 dc -- -- dc 500 -- -- -- 1.5 4.0 125 See note (3) 125 See note (3) 90 -- -- MAXIMUM 4.0 4.0 4.0 2.0 2.0 2.0 -- 1 100 100 -- -- -- -- -- -- -- 25 15 UNIT MHz MHz MHz MHz MHz MHz ns ms ms ms tCYC tCYC ns tCYC ns tCYC ns % % Freescale Semiconductor, Inc... 10 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS 10-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY 10 TPG 10-4 For More Information On This Product, Go to: www.freescale.com ELECTRICAL SPECIFICATIONS MC68HC05SU3A Freescale Semiconductor, Inc. 11 MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 40-pin DIP, 42-pin SDIP and 44-pin QFP packages for the MC68HC05SU3A. Freescale Semiconductor, Inc... 11 TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com MECHANICAL SPECIFICATIONS 11-1 Freescale Semiconductor, Inc. 11.1 40-Pin DIP Package (Case 711-03) 40 21 B 1 20 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 Freescale Semiconductor, Inc... A N C L J H G F D K SEATING PLANE M Figure 11-1 40-pin DIP Package 11.2 42-Pin SDIP Package (Case 858-01) -A42 22 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). -B1 21 L C H 11 -TSEATING PLANE F D 42 PL 0.25 (0.010) M G TA S N K J 42 PL 0.25 (0.010) M M TB S DIM A B C D F G H J K L M N INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 5.08 3.94 0.56 0.36 1.17 0.81 1.778 BSC 7.62 BSC 0.38 0.20 3.43 2.92 15.24 BSC 15 0 1.02 0.51 Figure 11-2 42-pin SDIP Package TPG 11-2 For More Information On This Product, Go to: www.freescale.com MECHANICAL SPECIFICATIONS MC68HC05SU3A Freescale Semiconductor, Inc. 11.3 44-pin QFP Package (Case 824A-01) L 33 34 23 22 S S D Freescale Semiconductor, Inc... D B -A,B,DB S 0.20 (0.008) M C A-B 0.05 (0.002) A-B -AL -BB V DETAIL A 44 1 11 12 0.20 (0.008) M H A-B S DETAIL A F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B BASE METAL S D S J S N D D S M DETAIL C DATUM PLANE 0.20 (0.008) M C A-B S D S SECTION B-B CE -CSEATING PLANE -HH 0.01 (0.004) G M M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.45 2.10 0.45 0.30 2.10 2.00 0.40 0.30 0.80 BSC 0.25 0.23 0.13 0.95 0.65 8.00 REF 10 5 0.17 0.13 7 0 0.30 0.13 12.95 13.45 0.13 0 12.95 13.45 0.40 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC 0.010 0.005 0.009 0.026 0.037 0.315 REF 10 5 0.005 0.007 7 0 0.005 0.012 0.510 0.530 0.005 0 0.510 0.530 0.016 0.063 REF T DATUM PLANE -H- R 11 K W X DETAIL C Q Figure 11-3 44-pin QFP Package TPG MC68HC05SU3A For More Information On This Product, Go to: www.freescale.com MECHANICAL SPECIFICATIONS 11-3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THIS PAGE LEFT BLANK INTENTIONALLY 11 TPG 11-4 For More Information On This Product, Go to: www.freescale.com MECHANICAL SPECIFICATIONS MC68HC05SU3A Freescale Semiconductor, Inc. GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS 1 2 3 4 5 6 7 8 9 10 11 Freescale Semiconductor, Inc... TPG For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS Freescale Semiconductor, Inc... 10 11 TPG For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com 15 1 2 3 4 5 6 7 8 9 Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... 10 11 12 13 14 15 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. 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